Various imager circuits have been proposed such as charge coupled device (CCD) arrays, complementary metal oxide semiconductor (CMOS) arrays, arrays combining both CCD and CMOS features, as well as hybrid infrared focal-plane arrays (IR-FPAs). Conventional arrays have light-sensing elements, typically referred to as “pixels” and readout circuitry that outputs signals indicative of the light sensed by the pixels.
A CMOS imager, for example, includes a focal plane array of pixel cells; each cell includes a photosensor (e.g., a photogate, photoconductor or a photodiode) overlying a substrate for producing a photo-generated charge in a doped region of the substrate. A readout circuit is provided for each pixel cell and typically includes at least a source follower transistor and a row select transistor for coupling the source follower transistor to a column output line. The pixel cell also typically has a floating diffusion region, connected to the gate of the source follower transistor. Charge generated by the photosensor is sent to the floating diffusion region. The imager may also include a transistor for transferring charge from the photosensor to the floating diffusion region and another transistor for resetting the floating diffusion region to a predetermined charge level prior to charge transference.
FIG. 1 illustrates a block diagram of a CMOS imager device 908 having a pixel array 200 with each pixel cell being constructed as described above, or as other known pixel cell circuits. Pixel array 200 comprises a plurality of pixels arranged in a predetermined number of columns and rows (not shown). The pixels of each row in array 200 are all turned on at the same time by a row select line, and the pixels of each column are selectively output by respective column select lines. A plurality of row and column lines are provided for the entire array 200. The row lines are selectively activated in sequence by a row driver 210 in response to row address decoder 220. The column select lines are selectively activated in sequence for each row activation by a column driver 260 in response to column address decoder 270. Thus, a row and column address is provided for each pixel.
The CMOS imager 908 is operated by a control circuit 250, which controls address decoders 220, 270 for selecting the appropriate row and column lines for pixel readout. Control circuit 250 also controls the row and column driver circuitry 210, 260 so that they apply driving voltages to the drive transistors of the selected row and column lines. The pixel output signals typically include a pixel reset signal Vrst taken off of the floating diffusion region when it is reset by the reset transistor and a pixel image signal Vsig, which is taken off the floating diffusion region after photo-generated charges are transferred to it. The Vrst and Vsig signals are read by a sample and hold circuit 265 and are subtracted by a differential amplifier 267, to produce a differential signal Vrst−Vsig for each pixel. Vrst−Vsig represents the amount of light impinging on the pixels. This difference signal is digitized by an analog-to-digital converter 275. The digitized pixel signals are fed to an image processor 280 to form a digital image output. The digitizing and image processing can be located on or off the imager chip. In some arrangements the differential signal Vrst−Vsig can be amplified as a differential signal and directly digitized by a differential analog to digital converter.
FIG. 2 illustrates a known four transistor (4T) CMOS imager pixel cell 102 and bias readout circuit 130 which may be utilized in pixel array 200. Pixel cell 102 includes a photodiode 110 connected to a transfer transistor 104. The transfer transistor 104 is also connected to floating diffusion region 108 which stores charge. A reset transistor 106 and a gate of source follower transistor 115 are connected to floating diffusion region 108. A row select transistor 119 is connected to source follower transistor 115. The active elements of pixel cell 102 perform the functions of (1) photon to charge conversion by photodiode 110; (2) resetting the floating diffusion region 108 to a known state before the transfer of charge to it by reset transistor 106; (3) transfer of charge to the floating diffusion region 108 by the transfer transistor 104; (4) selection of the cell 102 for readout by row select transistor 119; and (5) output and amplification of a signal representing a reset voltage (i.e., Vrst) and a pixel signal voltage (i.e., Vsig) based on the charges present on floating diffusion region 108 at reset and also after charge is transferred from photodiode 110 by source follower transistor 115.
When row select transistor 119 is turned on by a row select signal 118, source follower transistor 115 is connected to column readout line 116 which transfers the reset (Vrst) and pixel signal (Vsig) to a bias readout circuit 130. The bias readout circuit 130 contains a load transistor 120 which responds to bias voltage V1n, and functions as a current source when utilized in conjunction with bias transistor 125. As a result, source follower transistor 115 provides a voltage level on line 116 that reflects or follows the voltage level on the gate of source follower transistor 115. The reset (Vrst) and pixel signal (Vsig) on line 116 are sampled and held, subtracted (Vrst−Vsig) to produce a signal representing incident light which is then digitized and processed by an image processor.
FIG. 3 illustrates a comparison chart between a gate voltage for source follower transistor 115 and its output voltage. As shown in FIG. 3, when the gate voltage is, for example, 2.8 volts, the maximum output voltage of the pixel 102 is approximately 1.4 volts. This is due to voltage drops inherent in the source follower 115 and row select 119 transistors. Thus, the maximum swing of the pixel output voltage is 1.4 volts. This dynamic signal range may be inadequate in some applications.
Accordingly, there is a need and desire for a pixel readout circuit that has an increased output voltage swing for a pixel output signal for a given level of gate voltage on the source follower transistor.